About
Shubham Sharma
Staff R&D Engineer·Synopsys·Bengaluru, India
At Synopsys I work on synthesis and optimization for hardware-assisted emulation and verification. A design gets compiled into a netlist the emulator executes, and how good that netlist is decides both how much fits and how fast it runs. I work on the optimization algorithms in that flow, in C++.
Before that, four years on the backend of an automated media quality control platform. Some of that was performance work: analysis throughput, and a read path that had to be rebuilt once the files moved to object storage. A good deal of it was not. I designed and built a distributed task-processing architecture, and the process boundary that let a C++ product use Python-only AI models without becoming a Python application.
The scope widened as it went. Early on the unit of work was a function or a read path. Later it was the boundary between two runtimes, and debugging that ran from a frontend auth flow down into the backend. Now it is a compile flow where both runtime and memory are constrained.
I benchmark before deciding. Several of the calls I’m most confident about are ones where the obvious answer measured worse than what it was meant to replace: a newer library, a bigger model, a smaller buffer.
From media verification to hardware verification
Media verification and hardware verification are further apart on a résumé than they are in practice. Both are systems where a wrong answer is expensive and a slow answer is unusable.
2026
Apr 2026 — Present
Current
Bengaluru, India
Staff R&D Engineer
Synopsys
Netlist optimization for a hardware-assisted emulation platform, after moving from media verification into hardware verification.
- Work on netlist optimization algorithms in C++, including graph traversal and topological ordering over large design graphs.
- Added timing-driven resynthesis support, introducing consideration of timing constraints into a flow that previously optimized primarily for structural objectives such as depth and area.
- Work with lock-free multithreaded code, where memory behaviour is part of the algorithm rather than an afterthought.
Work from this period
2025
Jan 2025 — Mar 2026
Noida, India
Senior Software Engineer
Interra Systems
Took on cross-boundary architecture alongside the backend performance work, and debugging across the whole stack.
- Designed and implemented an IPC layer connecting a C++ client to a Python server, so the product could use Python-only AI libraries without embedding Python in the hot path.
- Debugged across frontend and backend layers, resolving SAML/OAuth encryption and decryption issues and correcting URL encoding in XHR workflows.
- Extended language identification support and integrated speech models into the analysis pipeline.
Work from this period
2022
Jul 2022 — Dec 2024
Noida, India
Software Engineer
Interra Systems
Backend engineering on an automated file-based media QC platform, focused on analysis throughput and cloud file access.
- Optimized automated QC analysis for MP4 and MXF through algorithmic and implementation-level changes in C++.
- Integrated AWS S3 CRT into the network file reader, using its multithreading and chunked reads to improve remote media-file access.
- Applied AVX intrinsics to image decoding, and designed a click-detection algorithm for audio signals.
- Designed and implemented a distributed task-processing architecture for splitting analysis work across a node fleet.
2022
Jan 2022 — Jun 2022
Noida, India
Software Engineer Intern
Interra Systems
Awards and internal contributions
Star Performance Award
Interra Systems
Awarded for consistently delivering complex features at pace while working on the BATON backend.
Recognition for Technical Excellence
Interra Systems
For contributions to multicore optimization, SIMD vectorization, and integrating AI models.
Internal technical report on AVX
Interra Systems
Wrote a paper for the team on how AVX accelerated workload performance, covering vector processing optimizations and efficiency.
Background
2022
BE, Computer Engineering
Thapar Institute of Engineering & Technology
CGPA 8.19
Get in touch
Open to conversations about systems and performance work: concurrency, algorithms, storage, and the places where correctness and speed have to hold at the same time.
- Location
- Bengaluru, India