Shubham Sharma
Staff R&D Engineer/Synopsys
I build and optimize high-performance systems in C++, where computation, concurrency, memory and I/O are the bottleneck.
Right now that means synthesis and optimization for hardware-assisted emulation and verification. Before that, four years on the backend of an automated media quality control platform.
Measured results
- Language identification accuracy
99.2%
Language identification accuracy
Up from 91.5% on a ~1,000-file evaluation corpus
- Faster media analysis
28.6%
Faster media analysis
ProRes 2160p · 17.6 GB · 4-core cloud instance
- Production model
138MB
Production model
2.9 GB alternative · Higher score on the same evaluation corpus
21× smaller
What I work on
Three problems keep recurring across media verification, distributed processing, and netlist optimization, in a different form each time.
Concurrency and parallel pipelines
Splitting work across cores or machines is the easy part. The design lives in what happens afterwards: ordering, contention, and what a system owes you when one worker dies mid-job.
I/O and storage performance
Storage has semantics, and code that assumes the wrong ones is merely slow locally and unusable remotely. Usually the fix is the access pattern rather than the code around it.
Algorithms close to the data
At a large enough scale, the shape of the data is the algorithm. How a structure is laid out in memory, and how much of it a traversal has to touch, decides the runtime.
Six problems worth writing up
Each one states what I personally did before it describes what the system does. Where a result was measured, the measurement and its conditions are shown; where it wasn't, no number is claimed.
- 01
Hardware-assisted emulation and verification
Synopsys·2026 — Present
Timing-driven resynthesis
A netlist optimization flow that improved structure without reasoning about timing, and the work to make timing constraints part of the decision.
Added timing-driven resynthesis support
C++Netlist optimizationGraph traversalTopological sortingLock-free multithreading - 02
Distributed systems
Interra Systems·2022 — 2024
Distributed processing architecture
Taking a single-machine media analysis engine and splitting one large job across a fleet of workers: queue, locking, ordered aggregation, and failure handling.
Designed and implemented the architecture from scratch
C++RedisDistributed lockingJob queuesFault handling - 03
Cloud storage performance
Interra Systems·2022 — 2024
S3 read optimization
A file reader written for local disks behaves badly against object storage. Rebuilding it around parallel, chunked reads changed the access pattern rather than the code around it.
Integrated S3 CRT with multithreaded, chunked reads
C++AWS S3S3 CRTAWS SDK for C++Multithreading - 04
Media processing and binary formats
Interra Systems·2022 — 2024
Reading less of the file
A multicore analysis pipeline was reading entire multi-gigabyte media files to compute information the container format already stored.
Designed and implemented the metadata-driven chunk mapping
C++MultithreadingMXF / KLVMOV / MP4ProRes22.3% / 28.6%
ProRes 2160p, 17.6 GB
- 05
AI integration and IPC
Interra Systems·2022 — 2026
AI language identification over IPC
The accurate model was Python-only and the product was C++. Three approaches were explored; the one that shipped moved the boundary instead of trying to erase it.
Selected the model and built the C++ to Python IPC layer
C++PythonNamed-pipe IPCWhisperFaster-Whisper99.2%
Accuracy
- 06
Measurement and engineering judgment
Interra Systems·2022 — 2026
Experiments and negative results
Four times the obvious answer was wrong. Measuring first is the only reason that was discovered before shipping rather than after.
Ran the benchmarks behind each decision
BenchmarkingAVX2 intrinsicsIntel IPPModel evaluation
How I work
Some of my work removes computation a system never needed. The rest is building what was not there yet.
Which of the two a problem needs is usually the first thing worth working out, and it is not always the one that looks obvious.
From media verification to hardware verification
Media verification and hardware verification are further apart on a résumé than they are in practice. Both are systems where a wrong answer is expensive and a slow answer is unusable.
2026
Apr 2026 — Present
Current
Bengaluru, India
Staff R&D Engineer
Synopsys
Netlist optimization for a hardware-assisted emulation platform, after moving from media verification into hardware verification.
Work from this period
2025
Jan 2025 — Mar 2026
Noida, India
Senior Software Engineer
Interra Systems
Took on cross-boundary architecture alongside the backend performance work, and debugging across the whole stack.
Work from this period
2022
Jul 2022 — Dec 2024
Noida, India
Software Engineer
Interra Systems
Backend engineering on an automated file-based media QC platform, focused on analysis throughput and cloud file access.
2022
Jan 2022 — Jun 2022
Noida, India
Software Engineer Intern
Interra Systems
Tools I've actually shipped with
Grouped by what they're for. Everything listed appears in work described on this site.
- 01Languages
- C++
- C
- Python
- 02Concurrency and SIMD
- Multithreading
- Lock-free structures
- Producer/consumer pipelines
- AVX2 intrinsics
- Intel IPP
- 03Storage and cloud
- AWS S3
- S3 CRT
- AWS SDK for C++
- Chunked / range reads
- Multipart upload
- Redis
- 04Algorithms and data structures
- Graph traversal
- Topological sorting
- Netlist optimization
- Timing analysis concepts
- Memory optimization
- 05Formats and protocols
- MXF / KLV
- MOV / MP4 / ISOBMFF
- ProRes, DNxHD, AVC-Intra, JPEG 2000
- HLS / DASH manifests
- IPC over named pipes
- 06AI integration
- Whisper
- Faster-Whisper
- Kaldi
- Voice activity detection
- 07Platforms
- Linux (Ubuntu, Rocky)
- Windows
Get in touch
Open to conversations about systems and performance work: concurrency, algorithms, storage, and the places where correctness and speed have to hold at the same time.
- Location
- Bengaluru, India